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资深架构设计师（ Sr. Architecture Engineer） |
电子邮箱： hr@shihong-micro.com |
发布日期： 2005-3-9 |
工作地点：上海市 |
招聘人数：2 |
性 别：不限 |
学 历： 硕士 |
工作年限： 2年以上 |
薪水范围：面议 |
外语要求：英语 |
接受简历的语言：中文或英文 |
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职位描述： |
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Job Description:
Chip architecture design in the field of audio and video DSP and compression/decompression
Required Skills:
Preferred MSEE minimum 5+year or PhD minimum 3+year experience in architecture design or digit IC design;
Familiar with CPU(MIPS or ARM)architecture;
Familiar with low power circuit architecture design
Familiar with audio and/or video standards, such as MP3, WMA, MPEG-2, MPEG-4, and H.264
Familiar with software development tools (Matlab/C/ C++, etc) and software/hardware co-design methodologies |
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IC销售（IC Sales） |
电子邮箱： hr@shihong-micro.com |
发布日期： 2005-3-9 |
工作地点：上海市 |
招聘人数：2 |
性 别：不限 |
学 历：本科 |
工作年限： 二年以上 |
薪水范围：面议 |
外语要求：英语 |
接受简历的语言：中文或英文 |
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职位描述： |
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协助销售经理与客户建立良好的合作关系，及时收集、分析市场信息
全面贯彻销售的基本活动，积极开拓新客户并完成销售指标
具有高度的敬业精神，出色的人际沟通能力
英语CET4级以上，读写、会话流利 |
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嵌入式软件工程师（ Embedded Software Engineer） |
电子邮箱： hr@shihong-micro.com |
发布日期： 2005-3-9 |
工作地点：上海市 |
招聘人数：4 |
性 别：不限 |
学 历： 硕士 |
工作年限： 一年以上 |
薪水范围：面议 |
外语要求：英语 |
接受简历的语言：中文或英文 |
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职位描述： |
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Job Description:
Embedded software system design, development and debug
Required Skills:
Preferred MSEE minimum 1+year experience in embedded software design.
Familiar with high performance RISC platform (such as ARM or MIPS) and development environment;
Familiar with audio and/or video standards decoder algorithm;
Familiar with embedded OS such as Linux; |
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数字 IC设计经理 |
电子邮箱： hr@shihong-micro.com |
发布日期： 2005-3-9 |
工作地点：上海市 |
招聘人数：1 |
性 别：不限 |
学 历：
硕士
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工作年限：
五年以上
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薪水范围：面议 |
外语要求：英语 |
接受简历的语言：中文或英文 |
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职位描述： |
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Job Description:
Project manage experience;
Fully understand the whole ASIC design flow;
Involved in all stages of product development including specification, design, verification, synthesis, timing, test pattern generation, backend verification and silicon debug;
Experience with digital signal processing, memory bus interface;
Required Skills:
Preferred MSEE minimum 4+year experience designing integrated circuits and experience with 1+ year project management;
Experience with ASIC design using Verilog and Synopsys Cadence verilog_XL, nc-sim Synopsys primetime, Design Compiler;
Familiar of HDL programming, EDA tools and IC design process;
Familiar of audio/video stardard;
Experience with audio/video IC design; |
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资深数字 IC设计工程师 （Sr. Engineer, Digital IC Design） |
电子邮箱： hr@shihong-micro.com |
发布日期： 2005-3-9 |
工作地点：上海市 |
招聘人数：5 |
性 别：不限 |
学 历： 本科 |
工作年限：二年以上 |
薪水范围：面议 |
外语要求：英语 |
接受简历的语言：中文或英文 |
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职位描述： |
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Job Description:
Project leading experience
Fully understand the whole ASIC design flow
Involved in all stages of product development including specification, design, verification, synthesis, timing, test pattern generation, backend verification and silicon debug
Experience with digital signal processing, memory bus interface
Required Skills:
Preferred BSEE minimum 3+year or MSEE minimum 2+year experience designing integrated circuits
Experience with ASIC design using Verilog and Synopsys Cadence verilog_XL, nc-sim Synopsys primetime, Design Compiler
Familiar of HDL programming, EDA tools and IC design process |
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资深嵌入式软件工程师（ Sr. Embedded Software Engineer） |
电子邮箱： hr@shihong-micro.com |
发布日期： 2005-3-9 |
工作地点：上海市 |
招聘人数：2 |
性 别：不限 |
学 历：
本科
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工作年限：三年以上 |
薪水范围：面议 |
外语要求：英语 |
接受简历的语言：中文或英文 |
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职位描述： |
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Job Description:
Embedded software system design, development and debug
Required Skills:
Preferred MSEE minimum 3+year experience in embedded software design.
Familiar with C/C++ program;
Familiar with high performance RISC platform (such as ARM or MIPS) and development environment;
Familiar with audio and/or video standards decoder algorithm and have experience in multimedia development (MP3, WMA, MPEG2, MPEG4);
Familiar with embedded OS such as Linux; |
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Full customer/Analog IC Layout Engineer |
电子邮箱： hr@shihong-micro.com |
发布日期： 2005-3-9 |
工作地点：上海市 |
招聘人数：2 |
性 别：不限 |
学 历：本科 |
工作年限：二年以上 |
薪水范围：面议 |
外语要求：英语 |
接受简历的语言：中文或英文 |
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职位描述： |
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Familiar with Vitruoso, Assura/Calibre.A proven track record in the sucessful design and physical implementation of high performance, PLLs, high speed A/D and D/A converters, from concept to product introduction, is preferred. Experience of assist backend management is prefered
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数字 IC设计工程师（Engineer, Digital IC Design） |
电子邮箱： hr@shihong-micro.com |
发布日期： 2005-3-9 |
工作地点：上海市 |
招聘人数：5 |
性 别：不限 |
学 历：本科 |
工作年限：二年以上 |
薪水范围：面议 |
外语要求：英语 |
接受简历的语言：中文或英文 |
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职位描述： |
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Job Description:
Familiar with the stages of product development including specification, design, verification, synthesis, timing, test pattern generation, backend verification and silicon debug
Required Skills:
Preferred BSEE minimum 2+year or MSEE minimum 1+year experience designing digital IC;
Experience with ASIC design using Verilog and Synopsys Cadence verilog_XL, nc-sim Synopsys primetime, Design Compiler
Familiar of HDL programming, EDA tools and IC design process |
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资深模拟 /混合信号IC设计工程师（Sr.Analog/Mixed signal IC designer） |
电子邮箱： hr@shihong-micro.com |
发布日期： 2005-3-9 |
工作地点：上海市 |
招聘人数：2 |
性 别：不限 |
学 历：本科 |
工作年限：二年以上
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薪水范围：面议 |
外语要求：英语 |
接受简历的语言：中文或英文 |
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职位描述： |
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A proven track record in the sucessful design and physical implementation of high performance, PLLs, high speed A/D, D/A converters and Power management from concept to product introduction, is preferred.
Design state of the art analog and mixed signal circuits for VLSI integration. Assist in defining functional and performance requirements. Assist product definition including specification, partitioning, architecture, project scheduling, tracking and resource estimations. Design custom analog and mixed signal blocks CMOS examples include very high performance ADCs, DACs, PLLs and signal conditioning circuits. Verification of performance requirements using appropriate simulation and verification tools. Experience in Analysis and design of analog, Experience in Ability of layout, verification guidance an debugging.
Required Skills:
Experience and Qualifications Required:
Transistor level circuit design in sub-micron CMOS. Types of circuits/systems designed are PLLs, VCOs, Filters, Bandgaps, Amplifiers, modulators, Power management, A/Ds, D/As, OP AMPs and references. Must have hands on experience using analog, mixed mode tools for schematic entry, layout entry/LVS and DRC verification. Practical lab debug experience and a proven track record in design and bringing to production of high performance PLLs, A/D's and D/A's is HIGHLY desirable |
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IC验证工程师（IC Verification Engineer） |
电子邮箱： hr@shihong-micro.com |
发布日期： 2005-3-9 |
工作地点：上海市 |
招聘人数：5 |
性 别：不限 |
学 历：本科 |
工作年限：一年以上 |
薪水范围：面议 |
外语要求：英语 |
接受简历的语言：中文或英文 |
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职位描述： |
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Job Description:
Engineers must have the right mix of hardware and software experience, who can help us develop environments and tools for verifying complex ASIC. They must be highly interested in working in a challenging digital circuit design/verification environment.
Required Skills:
Preferred BSEE minimum 2+year or MSEE minimum 1+year experience in IC verification;
At least 1-2 yrs in C Programming;
Minimum of 1-2 years with Verilog;
Must have basic working knowledge of how software simulators are use for Design of digital circuits.
Basic working knowledge of Unix or Linux scripting shells like csh,tcsh
At least 1 year Perl programming knowledge
Verification tools/languages like Vera, Testbuilder, System C, Specman
Knowledge of VCS, Modelsim, Verilog-XL or other HDL simulators is a plus. |
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P&R Layout Engineer/Sr.Engineer |
电子邮箱： hr@shihong-micro.com |
发布日期： 2005-3-9 |
工作地点：上海市 |
招聘人数： 2 |
性 别：不限 |
学 历：本科 |
工作年限：一年以上 |
薪水范围：面议 |
外语要求：英语 |
接受简历的语言：中文或英文 |
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职位描述： |
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Job responsibilities:
l.Deep sub-micron chip floor plan
CMOS 深亚微米芯片布局规划
2.CTS, Power plan, Placing & Routing, SDF
CTS, 布局布线, SDF
3.Whole chip DRC/LVS.
全芯片 DRC/LVS
Requirements:
1.College graduated or above, major in EE, CS, Physical or related
电子工程，计算机科学或物理学等相关专业大专以上学历
2.Four-year work experience in physical design including one year or
above in P&R
从事版图设计工作四年以上，其中一年以上的自动布局布线经验
3.Tape-out experience is preferred
有tape-out经验者优先
4.Familiarity with P&R tools of Synopsys, Cadence or Magma
熟悉Synopsys, Cadence或Magma的布局布线工具 |
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IC Layout Design Engineer / Manager (Shanghai) |
电子邮箱： hr@shihong-micro.com |
发布日期： 2005-3-9 |
工作地点：上海市 |
招聘人数： 1 |
性 别：不限 |
学 历：本科 |
工作年限：三年以上 |
薪水范围：面议 |
外语要求：英语 |
接受简历的语言：中文或英文 |
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职位描述： |
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Qualifications:
-BSEE or MSEE with 3+ year of directly related experience; Project leadership or management skills preferred
-Extensive experience with IC customer physical design; have successfully taped out at least 5 ICs including SOC and mixed-signal ICs (ADC, DAC, PLL etc).
-Familiar with place & route tools, commanding file writings;
-Knowledge in standard cell for custom chip design, floor planning, and full chip placement;
-Familiar with Scripts programming, UNIX, LINUX, C-Shell
-Experience with Apollo and Hercules from Avant!, Silicon Ensemble from Cadence.
-Very fluent in English writing, reading and speaking in the working environment |
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模拟/混合信号IC设计工程师（Analog/Mixed signal IC designer） |
电子邮箱： hr@shihong-micro.com |
发布日期： 2005-3-9 |
工作地点：上海市 |
招聘人数： 4 |
性 别：不限 |
学 历：本科 |
工作年限：一年以上 |
薪水范围：面议 |
外语要求：英语 |
接受简历的语言：中文或英文 |
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职位描述： |
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Job Description:
BSEE/MSEE 1+ years of experience;
Design and evaluation of CMOS analog circuits
Overseeing layout and verification activities, including floor plan, LVS and DRC
Experience in any of the following areas: Power management, PLL, A/D or D/A, high-speed I/O, VerilogA or AHDL, Matlab or C program preferred
Experience in Analysis and design of analog and RF building blocks
Experience in Ability of layout, verification guidance an debugging
Familiar with Cadence design environment
Job Description:
A proven track record in the sucessful design and physical implementation of high performance, PLLs, high speed A/D and D/A converters, from concept to product introduction, is preferred.
Design state of the art analog and mixed signal circuits for VLSI integration. Assist in defining functional and performance requirements. Assist product definition including specification, partitioning, architecture, project scheduling, tracking and resource estimations. Design custom analog and mixed signal blocks CMOS examples include very high performance ADCs, DACs, PLLs and signal conditioning circuits. Verification of performance requirements using appropriate simulation and verification tools. Experience in Analysis and design of analog, Experience in Ability of layout, verification guidance an debugging. |
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CAD 工程师 |
电子邮箱： hr@shihong-micro.com |
发布日期： 2005-3-9 |
工作地点：上海市 |
招聘人数：1 |
性 别：不限 |
学 历： 本科 |
工作年限： 2年以上相关工作经验 |
薪水范围：面议 |
外语要求：英语 |
接受简历的语言：中文或英文 |
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职位描述： |
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CAD Manager, Design Tech. Dept.
CAD工程师，设计技术部
Job responsibilities:
l.Design flow development
设计流程的发展
2.EDA tools support
EDA工具的技术支持
3.Design methodology improvement
设计体系的完善
Requirements:
l.Minimum bachelor degree, major in EE, CS, Physical
or related
电子工程，计算机科学或物理学等相关专业本科以上学历
2.Minimum five-year related experience with at least
one year management experience
2年以上相关工作经验
3.Perl / C-shell / TCL / Skill etc. scripts skills
撰写Perl / C-shell / TCL / Skill等编程脚本的技巧
4.Familiarity with EDA tools
熟悉各种EDA工具
5.Tape out support experience is preferred
有tape out技术支持经验者优先
6.Good interpersonal and communication skill both in
English and Chinese.
很好的人际关系，很好的中英文沟通技巧 |
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